Development of a wafer geometry measuring system : a double sided stitching interferometer

The drive for miniaturization of electrical devices and the increased production size of chips has forced lithographic production techniques to improve continuously. With this the requirements for silicon wafers, which form the basis of chips, have increased continuously as well. To ??nd a cost e??ective solution for the characterization of large diameter double side polished silicon wafers, the development of a measurement machine has been started. The measurement machine should measure the free form ??atness and thickness variations of wafers with a diameter of up to, and possibly beyond, 300 mm. The proposed measurement concept should have the potential to achieve a high throughput and a low measurement uncertainty, while reducing the cost of ownership signi??cantly compared to currently available systems on the market. The designed measurement setup which is described in this thesis is intended to demonstrate the potential of a chosen measurement concept for measuring double side polished silicon wafers. In the innovative measurement concept a double sided stitching Fizeau type interferometer has been adopted. A surface interferometer o??ers the required high accuracy and the scanning principle of a small aperture stitching interferometer allows the use of relatively small and low cost optical components which can measure with a high spatial resolution. The self referencing capability of a double sided Fizeau interferometer is important for achieving high accuracy when measuring thickness variations. In the proposed measurement concept the aperture of a single interferometer is split to measure the frontside and backside ??atness of a wafer simultaneously. The thickness variations can be derived from the measured ??atness measurements. A prototype measurement setup has been designed, built and tested. All major mechanical and optical error sources have been eliminated by using advanced calibration techniques. By using proper measurement principles and advanced software a robust and traceable wafer thickness and ??atness measurement instrument is created for measuring nominally ??at objects. The developed calibration techniques enable low uncertainty measurements to be taken while using relatively low quality optical and mechanical components. Several measurement method have been applied to derive accurate geometrical parameters from the recorded interferograms. Besides the processing of interferograms and development of calibration techniques a surface stitching software package has been developed which combines many subaperture ??atness maps into a large scale ??atness map of the entire wafer

Tailored Etch-Profiles of high aspect ratio trenches to prevent voids after refill with LPCVD sirn

A study is performed to obtain insight in etch- profile tailoring of high aspect ratio trenches (2 μm wide and 40 μm deep) to achieve void-free refilling with LPCVD SiRN. The trench profile obtained with Bosch DRIE is the most important factor determining formation of voids. Various Bosch recipes are characterized with respect to profile determining features and its applicability in void-free refilling

Nanometer resolution TEM sample manipulator for rotational and translational positioning

The design and fabrication process for a high performance manipulation stage for nanometer resolution TEM sample positioning over a 20 μm range is presented. A two level, planar stage is moved in three translational and three rotational directions by just two types of actuators; three horizontal and three vertical combdrives. The vertical combdrives are suspended by optimally designed torsion-beams, improving lateral stiffness by at least a factor of 50 compared to rectangular beams, hence minimizing the chance of electrostatic side pull-in

Fabrication scheme for dense aquatic flow sensor arrays

A fabrication scheme to realize dense arrays of flexible, closed membranes with a small gap separating them from the substrate is presented. These membranes are the first step towards aquatic hair based flow sensors biomimicking fish lateral line. Electrodes are integrated underneath the membrane to avoid contact with the liquid. Arrays of membranes with a diameter of 100 μm, gap height of 3 μm, and mutual distance of 200 μm have been successfully fabricated

Arithmetic Circuit Lower Bounds via MaxRank

We introduce the polynomial coefficient matrix and identify maximum rank of this matrix under variable substitution as a complexity measure for multivariate polynomials. We use our techniques to prove super-polynomial lower bounds against several classes of non-multilinear arithmetic circuits. In particular, we obtain the following results : As our main result, we prove that any homogeneous depth-3 circuit for computing the product of $d$ matrices of dimension $n \times n$ requires $\Omega(n^{d-1}/2^d)$ size. This improves the lower bounds by Nisan and Wigderson(1995) when $d=\omega(1)$. There is an explicit polynomial on $n$ variables and degree at most $\frac{n}{2}$ for which any depth-3 circuit $C$ of product dimension at most $\frac{n}{10}$ (dimension of the space of affine forms feeding into each product gate) requires size $2^{\Omega(n)}$. This generalizes the lower bounds against diagonal circuits proved by Saxena(2007). Diagonal circuits are of product dimension 1. We prove a $n^{\Omega(\log n)}$ lower bound on the size of product-sparse formulas. By definition, any multilinear formula is a product-sparse formula. Thus, our result extends the known super-polynomial lower bounds on the size of multilinear formulas by Raz(2006). We prove a $2^{\Omega(n)}$ lower bound on the size of partitioned arithmetic branching programs. This result extends the known exponential lower bound on the size of ordered arithmetic branching programs given by Jansen(2008).Comment: 22 page

Advanced spindle runout-roundness separation method

a flexible and accurate method for separating spindle error motion and workpiece roundness is presented. The method makes use of three or more displacement probes. Angle measuring probes can also be used. The angular positions of the probes as well as errors in sensor amplification are determined directly from the measurement data and require no extra measurements. The method can be used for real-time runout measurements with nanometer accuracy

Tuning a racetrack ring resonator by an integrated dielectric MEMS cantilever

The principle, fabrication and characterization of a dielectric MEMS cantilever located a few 100 nm above a racetrack ring resonator are presented. After fabrication of the resonators on silicon-on-insulator (SOI) wafers in a foundry process, the cantilevers were integrated by surface micromachining techniques. Off-state deflections of the cantilevers have been optimized to appropriately position them near the evanescent field of the resonator. Using electrostatic actuation, moving the cantilevers into this evanescent field, the propagation properties of the ring waveguide are modulated. We demonstrate 122 pm tuning of the resonance wavelength of the optical ring resonator (in the optical C-band) without change of the optical quality factor, on application of 9 V to a 40 µm long cantilever. This compact integrated device can be used for tuning/switching a specific wavelength, with very little energy for operation and negligible cross talk with surrounding device